Titre:
Signal Integrity and Board Design for Xilinx FPGAs
Conférencier:
Stéphane boyer ,
Hardent Inc., Canada
Lieu:
École Polytechnique de Montréal, Pavillon principal, B-401 ,
Date et heure:
jeudi le 15 avril 2010 de 09:00 à 17:00
Résumé:
Learn when and how to apply signal integrity techniques to high-speed interfaces. This comprehensive course combines design technique and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter. You will learn the basics of IBIS models and Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations.
Course Outline
Signal Integrity
Signal Integrity Introduction
Transmission Lines
IBIS Models and SI Tools.
Demo 1: Invoking HyperLynx
Reflections
Demo 2: Reflection Analysis
Crosstalk
Demo 3: Crosstalk Analysis
Signal Integrity Analysis
Power Supply Issues
Signal Integrity Summary
Note biographique: Stéphane Boyer is the chief operating officer and signal integrity specialist at Hardent Inc. a design services firm and Authorized Training Provider for Xilinx. He received the B.Eng. and M.Sc.A. degrees in electrical engineering from the École Polytechnique de Montréal, Canada, in 1997 and 2003 respectively. He has a varied background in ASIC and FPGA design with hands-on experience in medical, computer graphics and embedded systems applications.
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